1. Field of the Invention
The invention generally relates to processes for determining a layout for an integrated circuit from a netlist representing the circuit.
2. Description of Related Art
The rapid transition to a very deep submicro (VDSM) silicon process has created a significant demand for a change in design practices within the integrated circuit (IC) community. As process geometries are getting smaller, the finctionality that can be packed onto a single chip is increasing. The VDSM process enables designs measured in tens of millions of transistors. As the complexity of integrated circuits increases, the time required to lay out the circuity is dramatically increasing. To handle this level of complexity, designers are moving rapidly to a structured, hierarchical design implementation.
Full-custom integrated circuit layout is one of the last frontiers to be conquered by automation and is required to meet the increasing demands being made on custom designers. There is a need for tools to reduce design time for full custom blocks from months to weeks and even days, while maintaining the quality and performance of manual designs.
Furthermore, the time is rapidly approaching when manual full-custom integrated circuit layout schedules and time-to-market demands will be colliding. As consumer applications become the primary customer for the integrated circuit industry, time-to-market and design costs will be the primary design constraints. High quality automated layout solutions are needed to compete in this new consumer application environment.
While time-to-market concerns is rapidly becoming a critical design parameter, layout optimization in regard to area and performance remains critical. A need still exists for high quality automated layout solutions which can achieve compaction and performance levels that meet or exceed those achievable by manual layout.
Current automation tools appear to be cell-centric, regardless of the fact that interconnect parasitics dominate performance in deep sub-micron designs. As a further layer of impediment to the automation process, universal libraries are forced upon all designs, compromising area, timing, and power. Interconnect problems are dealt with in a reactive mode, since the automation or manual mentality provides minimal capability for interactive improvements.
A need therefore exists for an automated design tool that can produce integrated circuits with the density and performance of manual xe2x80x9cfull customxe2x80x9d design, and with the time to market and design throughput of the most efficient xe2x80x9csemicustomxe2x80x9d design. These and other needs are addressed by the methods of the present invention.
A computer implemented method is provided for forming a structural similarity group from a netlist of an integrated circuit comprising:
taking a netlist representation of components forming all or part of an integrated circuit;
forming groups of the components included in the netlist representation which have at least a selected degree of structural similarity between each other; and
forming a structural similarity group which includes those groups of components identified as having at least the selected degree of structural similarity.
A computer implemented method is also provided for forming a relative placement of components of an integrated circuit from a netlist comprising:
taking a netlist representation of components forming all or part of an integrated circuit;
forming groups of components within the netlist which have at least a selected degree of structural similarity between each other, those components within the netlist which do not have at least the selected degree of structural similarity being omitted from the groups of components formed;
performing an initial relative placement of the groups of components;
reducing wire lengths between components of initial relative placement; and
adding to the relative placement those components from the netlist which were not included in the groups of components.
A computer implemented method is also provided for modifying a relative placement of components of an integrated circuit comprising:
taking a relative placement of components of an integrated circuit;
analyzing adjacent components for resources associated with the components which can be shared; and
modifying the relative placement of components such that adjacent components share identified sharable resources.
A computer implemented method is also provided for determining at least part of a bus line routing for each bus line of an integrated circuit, each bus line routing including an initial routing and a cleanup routing, the method comprising:
taking a finalized relative placement of components of the integrated circuit, the placement including routing constraints and at least a first and second port locations associated with each bus line;
determining a routing order for the bus lines based on at least one criterion; and
determining an initial routing for each bus line based on the placement, each initial routing being substantially straight and substantially parallel to a bus line axis, a length of each initial routing based on a distance along the bus line axis between the first and second port locations, a position of each initial routing based on an average distance orthogonal to the bus line axis between at least the first and second port locations, wherein the placement is unaltered.
A computer implemented method is also provided for determining at least a part of a control line routing for each control line of an integrated circuit, each control line routing including an initial routing and a cleanup routing, the method comprising:
taking a finalized relative placement of components of the integrated circuit, the placement including routing constraints and at least a first and second port locations associated with each control line; and
determining an initial routing for each control line based on the placement, each initial routing being substantially straight and substantially parallel to a control line axis, a length of each initial routing based on a distance along the control line axis between the first and second port locations, a position of each initial routing based on an average distance orthogonal to the control line axis between at least the first and second port locations, wherein the placement is unaltered.
A computer implemented method is also provided for determining a cleanup line routing for a bus line or control line of an integrated circuit, the method comprising:
taking a finalized relative placement of components of the integrated circuit, the placement including routing constraints and port locations;
taking an initial routing for each bus line or control line; and
determining a cleanup line routing for each bus line or control line based on the placement and the initial routing, the cleanup line routing connecting the initial routing for each bus line or control line to ports associated with each bus line or control line.
An article of manufacture comprising a computer readable medium bearing a program code embodied therein for performing the above method and an integrated circuit design tool comprising: a processor; and memory coupled to the processor including instructions which when executed by the processor perform the above methods are also provided by the present invention.